Principal Physical Design Engineer

Responsibilities

• Lead the back-end design competence for disruptive NVM IPs targeting Automotive MCUs and MPUs
• Perform all functions in the RTL2GDS flow, including Synthesis, Floor-Planning, Power Distribution, Clock Tree Synthesis, Place and Route, ECOs, and Chip Finishing
• Execute Physical Verification and leverage AI tools to develop efficient, automated physical design flows
• Collaborate with global NVM design teams across Bangalore, Europe, and the US
• Mentor junior engineers to support growth within the NVM field

Requirements

• BS or MS in Electronics or Electrical Engineering
• 10+ years of experience in place and route design
• Hands-on experience with quality-managed Analog-Mixed signal design flows and tools (Cadence and Synopsys)
• Proven expertise in 1X/FinFET technology nodes and below
• Strong experience in scripting and flow automation

Preferred Qualifications

• Knowledge of NVM technology, macro architecture, and design
• Flexibility to work across both Cadence and Synopsys toolsets
• Excellent communication skills with experience working in international environments

About the Company

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As a world leader in secure connectivity solutions for embedded applications, NXP drives innovation across the automotive, industrial & IoT, mobile, and communication infrastructure markets.