Principal NoC IP Micro-Architect

Responsibilities

• Develop logic design, RTL coding, and simulation for Network on Chip (NoC) IPs and FPGA subsystems for full chip integration.
• Participate in the definition of architecture and microarchitecture features for designed blocks.
• Create prototypes, simulate models, and specify system requirements.
• Prepare and design logic diagrams and code to implement system design and test specifications.
• Deliver software models for device-level bring-up, including user-visible functionality, timing, and power.
• Apply RTL implementation techniques to meet power, performance, and area (PPA) goals in partnership with physical implementation teams.
• Utilize advanced EDA tools for timing constraints verification, RTL lint, CDC, RDC, and DFT to ensure high-quality IP development.
• Review verification plans and implement corrective measures for failing RTL tests to ensure feature correctness.
• Mentor and groom next-level technical members while overseeing the NoC team and proactively mitigating design challenges.

Requirements

• Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of related professional working experience.
• Extensive experience in Network on Chip (NoC) IP development.
• Proficiency in System Verilog and VCS/Synopsys simulators.
• Experience with Lint and Synthesis tools.
• Strong programming skills in C/C++, Perl, Python, TCL, and Unix Shell scripting.
• Excellent communication and problem-solving skills with the ability to collaborate across different teams.

Preferred Qualifications

• Experience in FPGA design and programming.
• Experience in RTL validation.
• Experience utilizing AI within the development process to enhance efficiency.

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products includes FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs, and IPUs.