Principal Engineer, Static Timing Analysis (STA)

About the Company

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. Their next-generation in-memory computing technology provides high compute efficiency and density for power and energy-constrained applications.

Responsibilities

• Drive the STA strategy for complex SoC and IP designs
• Develop and deploy solutions for timing closure, including sign-off margins and variation modeling (POCV/LVF)
• Lead the team through full-cycle STA from constraints validation to final GDS sign-off
• Act as the primary subject matter expert for Cadence Tempus, optimizing tool flows
• Partner with RTL, Synthesis, and Physical Design teams to influence floorplanning and CTS strategies
• Mentor the India team through code reviews and technical sessions

Requirements

• 14+ years of experience in VLSI
• Deep expertise in Signal Integrity (SI), Crosstalk, OCV/POCV/LVF, and SDC
• Mastery of Cadence Tempus (ECO, Tempus Stylus, and distributed timing)
• Proficiency in high-speed interface timing (DDR, PCIe) and low-power multi-voltage domains
• Advanced Tcl and Python skills for automation
• B.Tech/M.Tech in Electrical/Electronic Engineering or a related field

Preferred Qualifications

• Proven track record of leading high-impact teams in India
• Ability to debug complex timing paths and offer creative ECO solutions balancing PPA