Principal Engineer – Physical Design

Responsibilities

• Execute Full Chip APR and Physical Implementation (Netlist-to-GDSII) for hierarchical, low power, and mixed-signal designs
• Manage all aspects of physical design flows including floor planning, placement optimization, clock tree synthesis (CTS), and routing
• Lead full chip Physical Design activities and ensure crosstalk avoidance and physical verification
• Utilize sign-off tools for Static Timing Analysis (STA), Formal Equivalence, Parasitic Extraction, Power Integrity, and Physical Verification
• Collaborate with geographically diverse teams to achieve complex design goals and timing closure

Requirements

• Bachelor's or Master's Degree in Electrical or Electronics Engineering
• 10+ years of relevant experience in physical design
• Hands-on experience with physical design flows, including floor planning, placement, CTS, and routing
• Advanced knowledge of VLSI logic principles, clock structures, and design timing closure
• Experience with 40nm or 28nm technologies (16nm or smaller preferred)
• Knowledge of UPF and Low Power design practices throughout the physical design flow
• Proficiency in Tcl and Perl scripting
• Strong problem-solving, debugging, and communication skills

Preferred Qualifications

• Daily use of ICC/ICC2 or Innovus tools
• Experience with 16nm or smaller technology nodes

About the Company

Microchip Technology Inc. is a leading semiconductor company that develops technologies that power the world. With a team of over 17,000 members, we foster a culture of trust, empowerment, and innovation to deliver high-performance solutions to our global customers.