Principal Engineer, Physical Design

Responsibilities

• Complete entire physical implementation of the block and chip level
• Perform synthesis, floor-planning, power delivery, place & route, timing noise, physical verification, and IR/RV
• Collaborate with the SOC design team to drive architectural feasibility studies and develop timing, power, and area design targets
• Analyze the quality of the floorplan, customized clock tree structure, and place & route
• Implement ECOs for timing closure
• Perform Signal EM/Noise and Power IR/EM analysis and fixes
• Conduct DRC/LVS/ERC/ANTENNA analysis and clean up
• Manage timing and physical verification signoff

Requirements

• Master’s degree or above in electrical/computer science engineering with 10+ years of experience, or Bachelor’s degree with 15+ years of experience
• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification
• Expertise in the entire SOC implementation and verification flow from RTL-to-GDS
• Experience with Netlist (or RTL)-GDS physical implementation
• In-depth knowledge of major EDA tools and design flows
• Strong Cadence experience
• Experience with TSMC N22 or below technology
• Experience in chip integration and signoff
• Proficiency in Perl or TCL programming

Preferred Qualifications

• Strong experience in Low-power implementation methodology
• Strong experience in Advanced timing signoff methodology
• Knowledge of DFT (BSCAN, MBIST, SCAN) and its impact on physical design flows
• Ability to independently complete Netlist-GDS P&R and signoff tasks
• Proven record in multi-million gate design production tapeouts

About the Company

InnoPhase IoT is a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.