Principal Engineer - Digital ASIC Design

Responsibilities

• Lead the micro-architecture and RTL implementation of complex digital IP blocks using System Verilog from concept to delivery
• Drive Power, Performance, and Area (PPA) trade-offs and optimizations to meet aggressive product targets
• Collaborate with SoC integration teams to ensure seamless connectivity and address top-level timing and congestion issues
• Lead Lint, CDC, RDC, and formal verification efforts
• Work closely with Physical Design teams to close timing and resolve routing bottlenecks
• Cooperate with verification and validation teams to ensure module and system functionality
• Organize and maintain documentation to record all design activities

Requirements

• 10+ years of proven experience in ASIC or FPGA digital design
• BS or MS degree in Electrical Engineering
• Proficiency in System Verilog and a deep understanding of synchronous/asynchronous design techniques
• Experience with the full Cadence/Synopsys front-end EDA flow (e.g., VCS, SpyGlass, Design Compiler, PrimeTime)
• Post-silicon validation or bring-up experience, including proficiency with lab equipment like oscilloscopes and logic analyzers
• Ability to use scripting to improve design efficiency

Preferred Qualifications

• Familiarity with PHY or Serdes protocols
• Knowledge of IEEE 802.3 standards

Benefits

• Competitive base pay, restricted stock units, and quarterly bonus payments
• Health benefits starting on day one
• Retirement savings plans
• Industry-leading ESPP program with a 2-year look-back feature

About the Company

Microchip Technology Inc. is a leading semiconductor company that designs technology that powers the world. With a global team of over 17,000 members, we foster a culture of trust, empowerment, and innovation to deliver high-performance solutions across various industries.