Principal Engineer Design

Responsibilities

• Drive UPF methodology across frontend and backend teams for power intent and verification
• Work with Power Management Architects on feasibility studies
• Create and maintain workflows for early power estimation using EDA tools
• Define methods to derive UPF from higher-level abstractions and implement power intent verification at the chip level
• Partner with design and verification teams to troubleshoot and resolve UPF-related workflow challenges
• Collaborate with EDA vendors to define new power methodologies, automated UPF generation, and low power analysis
• Work within ASIC design flows, including RTL, verification, synthesis, and static timing analysis (STA)

Requirements

• 12+ years of relevant experience in semiconductor design
• Deep expertise in low-power design implementation, including UPF/CPF, multi-voltage domains, and power gating
• Strong understanding of ASIC and IP design flows
• Advanced scripting and programming skills in Python and TCL
• Hands-on experience with power analysis, estimation, and reduction tools (e.g., Power Artist, Prime-Power RTL, or Joules)
• Proficiency with low-power static checkers and power analysis optimization methods

Preferred Qualifications

• Experience with UPF-based synthesis and implementation
• Familiarity with CI/CD pipelines and software development methods
• Experience with tools such as GitLab, SonarQube, PyTest, VSCode, Git, and Perforce
• Knowledge of power-aware simulation (RTL/GLS) and system-level power modeling
• Understanding of mixed-signal power analysis, power islands, and isolation cell topology
• Experience with voltage regulators, including Buck and Low Dropout (LDO)

About the Company

Infineon is a global leader in semiconductor solutions for power systems and IoT. We enable game-changing solutions for green and efficient energy, clean and safe mobility, and smart and secure IoT, driving innovation to make life easier, safer, and greener.