Principal Engineer, ASIC/VLSI Synthesis and Design

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to analyze timing complexities and develop consolidated timing modes for synthesis and sign-off.
• Own front-end implementation tasks including Synthesis, UPF development, Logical Equivalence Checks (LEC), and Functional ECOs.
• Analyze tradeoffs between power, performance, and area (PPA) to drive chip implementation flows.
• Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler.
• Automate front-end flows and processes using scripting languages such as Tcl or Python.
• Ensure compliance with Netlist Handoff checklists for delivery to Physical Design.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 10-15 years of experience, OR a Master’s/PhD with 5-10 years of experience.
• Minimum of 5 years of industry experience in ASIC implementation and synthesis.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Hands-on experience with synthesis and STA methodologies and implementation.
• Proficiency in synthesis tools, STA tools, and scripting languages (Tcl, Python, or Perl).
• Experience with high-complexity silicon in advanced technology nodes (preferably TSMC N4/N5).
• Proven track record of delivering successful designs that meet performance, power, and area goals.

Preferred Qualifications

• Experience with UPF development and validation using tools like Conformal Low Power (CLP).
• Experience performing functional ECOs using industry-standard tools like Conformal ECO.
• Familiarity with physical design and timing optimization techniques for timing closure.

Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards.

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud, AI, and carrier architectures, our innovative technology is enabling new possibilities in the era of Accelerated Computing.