Principal Engineer, ASIC Development Engineering (STA and Sign-Off)

Responsibilities

• Own complete STA signoff for ASIC, providing direction and guidance to PnR teams for timing closure and synthesis report analysis
• Work with IP and Design teams on timing constraints development and review activities
• Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
• Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration
• Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
• Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations
• Prepare and present detailed timing reports and technical documentation to stakeholders

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Minimum of 8 years of experience in Static Timing Analysis (STA)
• Proven track record of successfully executing and owning STA signoff
• In-depth knowledge of STA tools such as Synopsys PrimeTime or Cadence Tempus
• Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
• Excellent problem-solving, analytical, and communication skills

Preferred Qualifications

• Experience with advanced process nodes such as 5nm or 3nm

About the Company

Sandisk understands how people and businesses consume data and relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world.