Principal Engineer, ASIC Development Engineering

Responsibilities

• Develop and maintain robust RTL integration flows, including IP stitching and hierarchical assembly
• Architect comprehensive RTL linting flows using industry-standard tools to ensure design quality
• Define and enforce CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) verification methodologies
• Develop and support RTL and gate-level ECO methodologies for late-stage design changes
• Implement early Power, Performance, and Area (PPA) estimation flows on RTL
• Create automation frameworks and regression infrastructure using scripting to improve productivity
• Lead tool evaluation and qualification for front-end CAD tools in collaboration with EDA vendors

Requirements

• Approximately 10 years of experience in front-end ASIC design, RTL integration, CAD, or methodology roles
• Strong understanding of RTL design principles, coding styles, and synthesizability
• Expertise in LINT, CDC, and RDC verification and signoff
• Proven experience with RTL and gate-level ECO methodologies
• Proficiency in scripting and automation using TCL, Python, Perl, or Shell
• B.Tech, M.Tech, or MS in VLSI Design, Electrical Engineering, Computer Engineering, or a related field

About the Company

Sandisk understands how people and businesses consume data and relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world.