Principal Engineer, ASIC Development Engineering

Responsibilities

• Own subsystem/block-level floorplanning and end-to-end place-and-route (PnR) flows for low-power, high-performance designs.
• Debug timing, power, and area issues, perform clock tree analysis, and contribute to full-chip timing convergence and closure.
• Collaborate with cross-functional teams, including Design and DFT, to streamline and enhance the PnR flow.
• Drive robust IP integration strategies to ensure high-quality ASIC delivery while minimizing schedule risks.
• Perform in-depth design and timing analysis to identify critical paths and implement mitigation strategies.
• Stay current with industry trends and emerging technologies in PnR to incorporate best practices into team workflows.
• Prepare and present technical analyses, reports, and documentation to stakeholders.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Minimum of 8 years of experience in the Place and Route (PnR) domain.
• Demonstrated track record of successful PnR execution across complex semiconductor projects.
• Strong expertise in industry-standard PnR tools such as Synopsys Fusion Compiler or Cadence Innovus.
• Solid understanding of digital design fundamentals, physical design concepts, and semiconductor fabrication processes.
• Strong analytical, problem-solving, and communication skills.

About the Company

Sandisk understands how people and businesses consume data and relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world.