Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout)

Responsibilities

• Develop and optimize MSIP IC layouts in TSMC 3nm technology, ensuring high performance and manufacturability
• Collaborate with design engineers to translate design requirements into precise layouts
• Independently debug DRC, ERC, LVS, EMIR, and PERC issues
• Work closely with the physical design team to integrate custom blocks into the overall chip design
• Identify and resolve layout-related issues and provide creative solutions to meet specifications
• Conduct design reviews and provide technical feedback to improve layout methodologies
• Stay up-to-date with industry trends, tools, and technologies to enhance layout processes

Requirements

• 8-12 years of experience in Analog/High Speed DDR IO IC layout design
• Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics
• Expertise in custom layout design for Bandgap references, LDOs, Clocking circuits, GPIOs, and High speed DDR IOs
• Advanced knowledge of CMOS and FinFET technologies (5nm and below)
• Experience with layout optimization for power, performance, and area (PPA) metrics
• Strong understanding of signal integrity, ESD, and latch-up mitigation techniques
• Bachelor’s or Master’s degree in Electronics or Electrical Engineering

Preferred Qualifications

• Knowledge of scripting languages such as Skill, TCL, and SVRF for automation tasks
• Prior AI knowledge or experience that can improve layout development effort and QoR

About the Company

Sandisk relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions are the beating heart of the digital world. We combine powerhouse manufacturing capabilities with an industry-leading portfolio of products recognized globally for innovation, performance, and quality.