Principal Digital Design Engineer

Responsibilities

• Propose, architect, and design RTL in Verilog for use in mixed-signal integrated circuits
• Apply clocking controls, FSM design, low power techniques, and high-speed design concepts
• Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking
• Participate in design, architecture, and verification reviews
• Create technical documentation for design, verification, and test teams
• Mentor and train junior engineers and New College Graduates

Requirements

• Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• 12+ years of direct experience in ASIC/IC design with deep knowledge of the entire IC design flow
• Expertise in Verilog RTL coding and ASIC design methodology
• Proficiency in static timing analysis and creation of place and route constraints
• Experience with logical synthesis and DFT insertion with high coverage
• Knowledge of CDC/RDC checking, formal verification, and linting
• Experience implementing and verifying ECOs on RTL, synthesized, and post-route netlists

Preferred Qualifications

• Familiarity with ATPG generation and ATE support
• Experience in DFT or physical design

About the Company

Renesas is an embedded semiconductor solution provider driven by the purpose "To Make Our Lives Easier." As a leading expert in embedded processing, we provide scalable semiconductor solutions for the automotive, industrial, infrastructure, and IoT industries. Our memory interface products team develops leading-edge digital sections for DDR5, DDR6, and beyond, serving high-performance AI and cloud computing data centers.