Principal DFT Engineer

Responsibilities

• Handle RTL Design for DFT related changes at both Subsystem and Top level Designs
• Insert and verify MBIST RTL for memories
• Analyze Scan DRCs and implement fixes in RTL
• Analyze ATPG reports on coverage, devise improvement mechanisms, and generate patterns for ATE
• Insert TAP, IOs, and Test Pinmux using NXP DFT flows
• Manage Power Aware RTL/GLS simulation bringup and maintain regression suites for Non-ATPG and ATPG simulations
• Collaborate with Product and Test teams to bring up patterns on Wafer probe and Final Test

Requirements

• 5+ years of experience in DFT implementation and verification
• Deep expertise in scan architectures, JTAG, memory BIST, and ATPG
• Strong understanding of Digital Design concepts
• Proficiency in Verilog or VHDL RTL coding
• Experience with Scan insertion, ATPG DRC, coverage analysis, and simulation debug with timing/SDF
• Ability to debug and root cause problems in simulation failures

Preferred Qualifications

• Experience working on leading-edge automotive, edge processing, or radar processing projects
• Proven ability to work in a self-driven, results-oriented environment

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a global leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial, IoT, mobile, and communication infrastructure markets.