Principal ASIC Physical Design Engineer

Responsibilities

• Own the complete RTL-to-GDSII flow including synthesis, floorplanning, place & route, CTS, STA, and physical verification
• Develop and maintain physical design methodologies, scripts, and automation to optimize PPA
• Drive timing closure across multiple voltage and process corners using foundry-qualified tools
• Partner with package, SI/PI, and test teams for package-aware floorplanning
• Manage and technically guide external physical design partners and service vendors
• Work with EDA vendors to debug and optimize tool flows
• Support chip bring-up, debug, and production through spaceflight

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC physical design for high-performance SoCs
• Proven end-to-end expertise in RTL-to-GDSII flows using Synopsys, Cadence, or Siemens tools
• Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs
• Experience with advanced FinFET process nodes
• Experience managing or coordinating offshore/outsourced PD teams or vendors
• Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF)

Preferred Qualifications

• Exposure to radiation-hardened or space-qualified ASICs
• Experience with chip-package co-design or advanced packaging (2.5D/3D)
• Experience driving tapeouts through TSMC
• Experience with Gate-All-Around technologies

About the Company

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by leading investors, K2 is mass-producing high-power satellite platforms for missions from LEO to deep space.