Principal Analog Layout Engineer

Responsibilities

• Develop block and macro level layouts including floor-planning, placement, routing, and optimization.
• Carry out layout feasibility studies in collaboration with senior analog designers to find optimal solutions.
• Write automation scripts for layout flow improvements, including pcells.
• Conduct thorough verification checks such as DRC, ANT, LVS, PERC, EM, and IR to ensure high quality.
• Debug ESD violations reported by PERC and suggest effective solutions.
• Investigate new features within layout tools to enhance productivity.
• Mentor junior layout team members and provide regular status updates to the group.

Requirements

• Bachelor's or higher degree in Electrical Engineering or a related field.
• 5+ years of relevant industry experience in custom analog and mixed-signal layout design.
• Strong knowledge of deep sub-micron CMOS devices (e.g., FinFET transistors).
• Proficiency in industry-standard tools such as Cadence Virtuoso, Siemens Calibre, or Ansys Totem.
• Expertise in layout techniques for floor planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, and ESD.
• High level of proficiency in interpreting DRC, PERC, ANT, PAD, ERC, and LVS.
• Solid understanding of RC delay, electromigration, and coupling effects.

Preferred Qualifications

• Scripting skills in PERL or SKILL.
• A proven history of successful analog circuit product deliveries.

Benefits

• Comprehensive medical, dental, and vision plans.
• Participation in DCPP (Canada) with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays, paid sick leave, and vacation time.

About the Company

Ciena is a global leader in high-speed connectivity, providing optical fiber transmission solutions and advanced telecommunications technology. We prioritize a people-first approach, fostering a flexible work environment that empowers individual growth, well-being, and belonging.