Power Integrity Senior Engineer

Responsibilities

• Design, optimize, and verify power delivery networks (PDN) for high-performance chips and electronic systems
• Perform PDN design, simulation, analysis, and debug for die, package, and board levels
• Derive PDN design budgets, including IR drops, droops, and PMIC requirements
• Conduct power integrity analysis for high-performance IPs and provide feedback for low-power chip and system architecture
• Work with package and board design teams to enable analysis and closure of PDN rails
• Define bump/BGA patterns for on-die power grid and decoupling capacitance analysis
• Perform lab measurements of PDN in both frequency and time domains
• Collaborate with system designers, design verification, and physical design teams to implement and verify power delivery
• Participate in the development of PDN methodology formulation

Requirements

• Masters, PhD, or Postdoc in Electrical/Electronics Engineering (ECE) or a related field
• 4-7 years of industry experience in power delivery network design and signal integrity analysis
• Expertise in signal and power integrity, specifically with on-die power grid design and decoupling capacitor analysis
• Proficiency with lab measurement equipment including VNA, spectrum analyzers, and oscilloscopes
• Strong understanding of analog and digital design, circuits, package, and PCB design
• Knowledge of power, timing, and IR drop issues in lower tech nodes

Preferred Qualifications

• Experience with AI/ML techniques to extrapolate and predict traditional electrical behavior
• Proficiency in programming languages such as Python, TCL, or C
• Experience with industry-standard toolsets including Cadence APD, Voltus, PowerSi, Ansys HFSS, Q3D, SiWave, HSpice, ADS, or Matlab

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future.