Power-Domain Verification Lead

Responsibilities

• Execute power-aware simulations and debug failures related to power intent
• Integrate UPF with UVM testbenches and VIPs
• Verify design at RTL (SOC) level and gate-level simulation
• Create directed and constrained-random tests for low-power scenarios
• Verify power gating, isolation, retention save/restore, and reset behavior across power domains
• Develop assertions and functional coverage for power states and transitions
• Support power-aware regression and sign-off
• Collaborate with RTL and power architects

Requirements

• 10+ years of experience with strong hands-on experience with SystemVerilog & UVM
• Solid understanding of UPF / power intent modeling
• Experience with power-aware simulation
• Knowledge of power domains, power states, isolation, retention, and level shifters
• Strong debug skills across RTL, UPF, and testbench
• Proficiency in scripting languages such as Make, Perl, Python, or Shell
• BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent

About the Company

Axiado is building the future of AI-powered digital infrastructure. We are a fast-growing, well-funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI-driven resilience, and real-time platform management.