Power Consumption Engineer

Responsibilities

• Own the power budget for next-gen SoC designs, bridging the gap between IP owners and system architects
• Define and negotiate power consumption targets per IP and HW partition
• Lead Model HW analysis for leakage and dynamic power optimization
• Support thermal analysis for SoC targets and ensure signoff for complex power management features
• Manage end-to-end power consumption from architectural definition to silicon measurements
• Partner with concept and system design teams to drive low-power strategies and platform decisions
• Own and enhance internal Power Target Setting and Power Estimator tools
• Serve as Power Track Lead within Agile/Scrum development environments

Requirements

• Minimum 15+ years of relevant industry experience in the semiconductor domain
• Deep expertise in low-power design techniques (clock gating, power gating, multi-Vt optimization, DVS/DVR)
• Strong hands-on experience across the full digital design lifecycle (design, verification, synthesis, and physical layout)
• Proven experience with power estimation tools and correlation with thermal analysis and silicon behavior
• Proficiency in scripting languages such as Python or Tcl for tool automation and workflow optimization
• Strong stakeholder management skills to align cross-functional groups and IP teams

About the Company

Infineon is a global leader in semiconductor solutions for power systems and IoT. We enable game-changing solutions for green and efficient energy, clean and safe mobility, and smart and secure IoT, driving innovation to make life easier, safer, and greener.