PNR Applications Engineer, Staff

Responsibilities

• Support the sale and adoption of Synopsys products by helping customers achieve performance improvements in chip design cost, quality, and development time
• Provide expertise in ASIC design using industry-standard tools for Placement, Optimization, CTS, and Routing
• Utilize Synopsys back-end tools for Logical and Physical Synthesis, AI methodologies, Timing Closure, and Static Timing Analysis
• Assist customers in exploiting new technologies and navigating advanced node methodologies
• Manage multiple customer issues simultaneously while maintaining high levels of customer sensitivity and priority setting

Requirements

• BSEE with 7+ years of experience or MSEE with 5+ years of experience
• Extensive experience in ASIC design and implementation
• In-depth knowledge of Synopsys back-end tools and advanced node routing
• Proficiency with back-end P&R tools such as Fusion Compiler or ICC2
• Strong understanding of RTL to GDSII full flow
• Excellent verbal and written communication and presentation skills

Preferred Qualifications

• Knowledge of Clock Tree Synthesis methodologies like H-Tree or MS-CTS
• Experience with front-end Synthesis tools including Design Compiler or Genus
• Proficiency with Static Timing Analysis (STA) tools such as PrimeTime or Tempus

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Eligibility for annual bonuses and equity
• Competitive total rewards package based on location, skills, and experience

About the Company

Synopsys is a global leader in chip design, verification, and IP integration. We drive the innovations that shape the way we live and connect, providing the essential technology for the Era of Pervasive Intelligence, from self-driving cars to learning machines.