Place and Route Design Automation Engineer

Responsibilities

• Develop and support automated Place & Route (P&R) tools, flows, and methodologies for next-generation FPGA silicon development
• Maintain and improve existing P&R automation flows and infrastructure
• Develop and enhance scripts and automation utilities using Tcl, Perl, or Python to improve efficiency and scalability
• Provide end-user support for flow tools, including debugging issues and promoting best practices
• Support improvements in P&R quality of results, including timing, power, congestion, and density
• Identify design or flow bottlenecks and implement practical optimizations
• Collaborate with cross-functional teams across physical design, RTL, synthesis, and CAD to ensure robust end-to-end flow support
• Document methodologies, flow updates, and usage guidelines

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
• 3+ years of experience in semiconductor design or design automation
• 3+ years of hands-on experience in Place & Route (P&R) or physical design
• 3+ years of experience with industry-standard EDA tools (e.g., Synopsys, Cadence)
• 3+ years of coding experience in Tcl, Perl, or Python for automation and scripting
• 3+ years of experience in Unix/Linux development environments
• 3+ years of experience with physical design fundamentals, including floorplanning and static timing analysis (STA)

About the Company

Altera is a leading supplier of programmable hardware, software, and development tools that empower designers of electronic systems to innovate and succeed. With a broad portfolio of industry-leading FPGAs, SoCs, and design solutions, Altera enables customers to achieve faster time-to-market and exceptional performance in applications spanning aerospace, defense, cloud data centers, automotive, and edge AI.