Physical Design/PnR Lead

Responsibilities

• Implement RTL to GDS2 flow, including floorplanning, power-plan, synthesis, placement, CTS, routing, and extraction
• Handle physical verification (DRC & LVS), crosstalk analysis, EM/IR, and formal equivalence
• Perform full chip level tasks such as bus/pin planning, feed-thru planning, and parasitic extraction
• Utilize PnR tools including Synopsys Fusion Compiler, ICC2, PrimeTime, and Cadence Innovus
• Identify complex technical problems and drive hands-on flow development and scripting to automate design processes

Requirements

• 8+ years of professional experience in physical design, preferably with high-performance designs
• Proven experience in RTL to GDS2 flow implementation
• Experience with FinFET and Dual Patterning nodes (e.g., 16/14/10/7/5nm)
• Proficiency with industry-standard tools: Synopsys Fusion Compiler, ICC2, PrimeTime, and Cadence Innovus
• Bachelors or Masters degree in Computer Engineering or Electrical Engineering

Preferred Qualifications

• Experience in automated synthesis and timing-driven place and route for high-speed datapath and control logic
• Expertise in clock tree synthesis, clock/power gating techniques, and scan stitching
• Strong background in static timing analysis and design optimization for power, performance, and area (PPA)
• Versatility with scripting for design flow automation
• Good understanding of computer organization and architecture

About the Company

AMD is a global leader in high-performance computing, graphics, and visual technologies. Our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers to PCs, gaming, and embedded systems. We strive for execution excellence through a culture of innovation, collaboration, and inclusion.