Physical Design Timing Engineer

Responsibilities

• Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon
• Use and develop AI-assisted tool flows to accelerate physical design timing convergence and signoff timelines
• Work with chip-design and software teams driving the AI accelerator program from first silicon through scale-out

Requirements

• 10+ years of experience on very high performance designs at advanced technology nodes (7nm or better)
• Expertise in 2.5D/3D timing flows
• Exceptional abilities across the full physical design flow including synthesis, place & route, CTS, and signoff
• Hands-on experience with industry-standard PD tools such as Cadence Innovus or Synopsys Fusion Compiler
• Proficiency with signoff tools like PrimeTime or Tempus
• Ability to work closely with architects, RTL designers, EDA vendors, and foundries

Preferred Qualifications

• Post silicon characterization and process targeting experience
• Multi-die packaging (CoWoS, 2.5D / 3D)
• Thermal, IR, or EM signoff experience
• Signal integrity or DFT-aware physical design knowledge

Benefits

• Equity grant per company guidelines
• Medical, dental, and vision insurance
• 401(k)
• Standard PTO
• Visa sponsorship support