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Posted 10 hours ago
Physical Design Intern
EtchedPD Intern
Perks & benefits
Paid LeaveHousing AllowanceRelocation Allowance
Requirements
Degree progress in EE or CE, High-speed digital logic familiarity, ASIC or SoC design exposure, SystemVerilog, UVM, or Python familiarity, Physical design flow familiarity
Skills
ASICSystemVerilog
About the role
About the Company
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.
Responsibilities
- Realize front-end designs in silicon
- Assist in developing and running Physical Design flows to synthesize blocks
- Automate final design checks
- Advise RTL design decisions
Requirements
- Progress towards a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or a related field
- Familiarity with high-speed digital logic
- Exposure to ASIC or SoC design concepts
- Familiarity with SystemVerilog, UVM, or Python
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Ability to learn quickly about transformers and modern AI
Preferred Qualifications
- Familiarity with modern ML and LLM model architectures
- Familiarity with numerical representations and functions (RTL)
- Familiarity with clocking and reset schemes (RTL/PD)
- UVM or formal verification experience (DV)
- Ability to program with Python or another scripting language
Benefits
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Direct mentorship from industry leaders and world-class engineers
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Get started — it's freePhysical Design Intern
Etched · San Jose
