Physical Design Engineer, Staff

Responsibilities

• Design and implement RTL to GDS flows for on-chip silicon lifecycle monitors, including process, voltage, temperature, glitch, and droop sensors
• Own the digital backend process from synthesis through tapeout, including floorplanning, power planning, placement, CTS, and routing
• Manage multivoltage design using UPF and VCLP
• Develop and close pre-layout and post-layout STA across multiple corners using PrimeTime and PrimeTime PX
• Execute physical verification and signoff tasks including DRC, LVS, PERC, ERC, antenna checks, and EMIR using ICV and RedHawk
• Build and refine design flows through automation scripting in TCL and Perl
• Generate timing and DRV ECOs to meet aggressive PPA targets on advanced FinFET and GAA nodes

Requirements

• Bachelor's or Master's degree in Electrical Engineering
• 5+ years of experience in physical design, physical verification, and STA at the IP, block, or full-chip level
• Proven success with tapeouts on advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, or 2nm)
• Proficiency with Synopsys toolsets: Fusion Compiler, VCLP, PrimeTime, PrimeTime PX, ICV, and RedHawk
• Strong understanding of multivoltage design, UPF, SDC constraints, OCV, POCV, and crosstalk
• Experience scripting in TCL and Perl to automate design flows

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and regional retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across a wide range of industries.