Physical Design Engineer

Responsibilities

• Own floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon
• Use and develop AI-assisted tool flows to accelerate physical design and signoff timelines

Requirements

• 8+ years of experience on very high performance designs at advanced technology nodes (7nm or better)
• Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff)
• Hands-on with industry-standard PD tools such as Cadence Innovus or Synopsys Fusion Compiler
• Experience with signoff tools like PrimeTime or Tempus
• Ability to work closely with architects, RTL designers, EDA vendors, and foundries

Preferred Qualifications

• Multi-die packaging (CoWoS, 2.5D / 3D)
• Thermal / IR / EM signoff
• Signal integrity
• DFT-aware physical design

About the Company

DensityAI is developing AI accelerator silicon to drive high-performance computing programs from first silicon through scale-out.