Physical Design Engineer

Responsibilities

• Work on the design and analysis of 3D integrated products and novel wafer-scale architectures
• Combine traditional ASIC/SoC physical design skills with packaging, power, clock, and cooling analysis
• Partner closely with architecture and RTL teams to conduct R&D on novel 3D integration concepts
• Optimize designs for the best possible power, performance, and area (PPA)
• Resolve complex block and full-chip DRC and LVS issues

Requirements

• 10+ years of physical design and verification experience
• Expertise in the complete physical design flow
• Strong knowledge of block-level and full-chip physical verification methodology
• Proficiency with ICV or Calibre tools for DRC and LVS resolution
• Expertise in IR/EM analysis and resolution
• Experience with 3D physical design, including 3D die stacking, 3D chip design, or die-to-die/wafer-to-wafer architectures
• Strong scripting skills in Tcl and Python to enhance design flows
• Proven ability to work with RTL teams to optimize for physical design

Preferred Qualifications

• Experience performing full chip floor planning and integration
• Knowledge of clock distribution techniques
• Knowledge of cooling analysis

About the Company

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, empowering machine learning users to effortlessly run large-scale ML applications. Our technology is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via ultra high-speed inference.