NSP STA/Timing Engineer

Responsibilities

• Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs
• Conduct timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus
• Run PrimeTime and/or Tempus for STA flow optimization and Spice to STA correlation
• Evaluate multiple timing methodologies and tools across different designs and technology nodes
• Develop automation scripts within STA/PD tools for methodology development
• Collaborate with cross-functional teams to meet performance requirements and ensure successful product launch

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field
• 3+ years of Hardware Engineering experience (or Master's with 2+ years, or PhD with 1+ year)
• Proficiency in design automation using TCL, Perl, or Python
• Familiarity with digital flow design implementation (RTL to GDS) using tools like ICC or Innovus
• Experience with STA tools such as PrimeTime or Tempus
• Knowledge of process technology enablement, including circuit simulations using Hspice/FineSim and Monte Carlo

Preferred Qualifications

• 5 - 15 years of specialized experience in STA/Timing
• Strong expertise in AOCV/POCV concepts, CTS, and managing timing constraints
• Experience driving timing convergence at both Chip-level and Hard-Macro level
• In-depth knowledge of cross-talk noise, Signal Integrity, and Layout Parasitic Extraction
• Proficiency in scripting languages including TCL, Perl, and Awk
• Basic knowledge of device physics and Spice simulation

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future.