NPU/AI Processor Synthesis Sr Staff Engineer

Responsibilities

• Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools like Synopsys Design Compiler or Cadence Genus.
• Drive pre-layout and post-layout timing closure across multiple voltage and process corners.
• Optimize for aggressive PPA (Performance, Power, Area) targets using physical-aware synthesis techniques.
• Implement low-power design strategies utilizing UPF/CPF flows.
• Validate and maintain SDC constraints for clocks, I/O delays, and multi-cycle paths.
• Collaborate cross-functionally with RTL design, DFT, and physical design teams to ensure seamless handoffs.
• Perform quality checks including LEC (Logical Equivalence Check), CLP, and linting.
• Mentor junior engineers and drive best practices across synthesis and timing teams.

Requirements

• 12+ years of experience in ASIC synthesis and timing closure.
• At least 2 years of direct experience in NPU or AI processor design.
• Strong knowledge of the full ASIC design flow (RTL → Synthesis → STA → P&R).
• Proficiency with synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).
• Advanced scripting skills in Tcl, Perl, or Python for automation.
• Extensive experience with low-power design and UPF/CPF-based flows.
• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

• Experience working with advanced technology nodes (5nm/3nm).
• Expertise in hierarchical synthesis and physical-aware flows.
• Proven track record of successful tape-outs for NPU or DSP cores.

About the Company

Qualcomm is a global leader in wireless technology, developing end-to-end solutions that power the world's most advanced mobile and connected devices. We foster a culture of innovation, where the brightest minds work together to solve the most complex engineering challenges.