NPU Physical Design Engineer Sr Staff

Responsibilities

• Complete ownership of PNR implementation including Floorplanning, Placement, CTS, and post_route on latest nodes
• Execute PNR implementation for Qualcomm Hexagon NPU
• Perform signoff tasks including STA, Power analysis, FV, low power verification, and PV
• Collaborate with cross-functional teams to meet performance requirements

Requirements

• 12+ years of experience with PNR flow in latest tech nodes (e.g., 4nm, 5nm, 7nm, 10nm)
• Hands-on experience with Floorplanning, PNR, and STA flows
• Knowledge of Placement, Clock Tree Synthesis (CTS), and optimization
• Understanding of signoff domains such as LEC, CLP, and PDN
• Proficiency in Unix/Linux and Perl/TCL scripting fundamentals
• Strong analytical and problem-solving skills

Preferred Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field
• Master's degree or PhD in related engineering fields

About the Company

Qualcomm is a leading technology innovator driving digital transformation to create a smarter, connected future through cutting-edge hardware and wireless solutions.