NoC Interconnect Design Engineer and Architect

Responsibilities

• Create micro-architecture bus component specifications and analyze performance results
• Deliver RTL and manage tool flows for large SoC projects
• Evaluate new IPs and drive new protocol deployments
• Define system-wide guidelines for IP interoperability within the SoC
• Support verification, silicon validation, and software teams to ensure successful interconnect deployment

Requirements

• Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, or integration experience (or Master's with 1+ year, or PhD)
• Strong knowledge of bus protocols such as AHB, AXI, and CHI
• Proficiency in ASIC flows, including synthesis, STA, and Lint
• Experience with RTL design, FPGA, and post-silicon debug
• Strong troubleshooting and problem-solving skills
• Ability to perform architecture tradeoff analysis regarding performance, power, and area

Preferred Qualifications

• Familiarity with CPU architecture
• Experience with power analysis tools and Network on Chip (NoC) architectures

About the Company

Qualcomm Technologies, Inc. is a global leader in wireless technology, driving innovation in mobile, automotive, and Internet of Things (IoT) sectors. We hire the brightest minds to solve the world's most complex technical challenges.