MTS ASIC Architect

Responsibilities

• Lead architectural trade-off analysis across DRAM silicon, ASIC logic, packaging, and system integration
• Influence functional partitioning and interface definition to optimize performance, power, and scalability
• Drive architectural analysis including PPA evaluation, IO timing, and scalability paths for next-generation products
• Perform micro-architectural, RTL, and design reviews to ensure high-quality execution and first-silicon success
• Serve as a technical mentor and architectural authority for execution teams to elevate technical rigor
• Influence cross-functional decisions through data-driven analysis and deep architectural insight

Requirements

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Approximately 15 years of professional experience
• Proven experience in SoC or Subsystem micro-architecture/architecture and leading technical definitions
• Extensive experience in high-speed digital logic design
• Deep understanding of DRAM architecture, including trade-offs in bandwidth, latency, power efficiency, and reliability
• Demonstrated technical leadership, mentoring, and ability to work independently in ambiguous environments

Preferred Qualifications

• Master’s or PhD degree in a relevant engineering or computer science field
• Experience with multi-die interfaces
• Experience collaborating across DRAM silicon, ASIC logic, packaging, and high-speed interfaces
• Experience engaging with customers, ecosystem partners, or industry standards organizations like JEDEC
• Familiarity with system-level trade-offs involving performance, power, signal integrity, and thermals

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. We deliver a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products that fuel the data economy and enable advances in artificial intelligence and 5G applications.