Mixed Signal Design Engineer

Responsibilities

• Design high-precision Sigma-Delta DACs and ADCs for control and monitoring
• Develop SystemVerilog models for various analog macros
• Design IBIS-AMS models for high-speed DAC and ADC based SerDes IP (56Gbd to 448Gbd)
• Create comprehensive Design Specification Documents
• Collaborate with system, analog, digital, DSP, signal integrity, hardware, firmware, and analog lab teams

Requirements

• Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related scientific field (BEng/BSc, MEng/MSc, or PhD)
• Proven design experience in latest CMOS and BiCMOS technologies
• Proficiency with Cadence Virtuoso, Xcelium, and AMS
• Familiarity with SystemVerilog, VerilogAMS, VerilogA, Matlab/Simulink, C/C++, or Python
• Strong ability to work both independently and collaboratively
• Professional proficiency in written and spoken English

Preferred Qualifications

• Knowledge of UVM, Git, Gradle, and Google Tests
• Experience with RF and Signal Integrity tools
• Experience with DSP, digital, and analog design/modelling in high SerDes applications
• Experience using AI tools for automation

Benefits

• Competitive annual salary range ($90,600 - $144,800 CAD)
• Comprehensive medical, dental, and vision plans
• Retirement savings plan (DCPP in Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Paid sick leave, vacation time, and company-paid holidays
• Employee Assistance Program (EAP)

About the Company

Ciena is a global leader in high-speed connectivity and optical fiber transmission solutions. We are a technology company that leads with humanity, prioritizing a flexible work environment that empowers individual growth, well-being, and belonging.