Mixed Signal Custom Layout Engineer

Responsibilities

• Create clean, robust layouts for digital and analog building blocks at the transistor level using Cadence Virtuoso
• Floorplan, route, and assemble lower-level cells into macros
• Build black-box/abstract models and views for other teams and contribute to tapeout collateral
• Run hierarchical physical verification checks including DRC, LVS, ERC, EM/IR, and Latch-up/ESD
• Iterate design to closure in partnership with circuit owners
• Explore and leverage AI-assisted tools and workflows to improve layout productivity and design quality

Requirements

• Electrical or Mechanical Engineering degree (or related Electronics diploma)
• 2-3 years of experience in custom layout design
• Proficiency with industry-standard tools such as Cadence Virtuoso and Calibre
• Strong understanding of CMOS device/circuit theory and analog/digital layout best practices
• Experience with physical verification flows including DRC, LVS, and EMIR

Preferred Qualifications

• Exposure to advanced process nodes (e.g., 2nm, 3nm, 5nm, or 7nm)
• Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, or DACs
• Experience with scripting and automation using Perl, TCL, SVRF/TVF, or SKILL

About the Company

AMD is on a mission to build great products that accelerate next-generation computing experiences—from AI and data centers to PCs, gaming, and embedded systems. We push the limits of innovation to solve the world’s most important challenges through a culture of collaboration and execution excellence.