Mixed-Signal AMS Co-Simulation Verification Engineer

Responsibilities

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments.
• Perform functional verification of SERDES blocks, including TX/RX data paths, equalization algorithms, and PLL locking.
• Debug and resolve simulation failures across analog, digital, and mixed-signal domains.
• Conduct design reliability checks such as electromigration (EM) and IR analysis.
• Collaborate with mixed-signal designers and system architects across global teams.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, etc.).
• Exposure to Verilog or System Verilog and AMS concepts.
• Experience with AMS tools such as HSPICE, XA, Custom Sim, or VCS.
• Proficiency in scripting languages like Python, Perl, or UNIX shell.

Preferred Qualifications

• Experience with UVM (Universal Verification Methodology).
• Ability to debug complex analog-digital interactions.
• Experience in high-speed SERDES or mixed-signal verification.

Benefits

• Comprehensive medical and healthcare plans.
• Paid time away including ETO and FTO programs.
• Family support including maternity/paternity leave and adoption assistance.
• Employee Stock Purchase Plan (ESPP) with a 15% discount.
• Competitive retirement plans and salaries.

About the Company

Synopsys is the global leader in EDA tools, semiconductor IP, and silicon engineering solutions. We empower the creation of the world’s most advanced chips across AI/ML, high-performance computing, automotive, cloud, and mobile applications.