Memory Cell Test Structure Design and Layout Engineer

Responsibilities

• Design and layout memory cell and support circuitry-based test structures for advanced technology nodes
• Collaborate with cross-functional teams including Process Integration, Electrical Characterization, Device, Reliability, and CAD
• Support process development through interaction with mask development, OPC, product, and design teams
• Verify and validate test structure documentation and parametric data
• Assist with parametric correlation and debug activities

Requirements

• Master’s degree in Electrical, Computer, or Microelectronic Engineering
• Hands-on experience with EDA tools such as Cadence Virtuoso (Layout and Schematic Editor) and Calibre
• Strong skills in circuit design, layout, schematic, and verification (DRC, LVS, and HSPICE)
• Solid knowledge of semiconductor device physics, operation, parametric testing, and DFM
• Familiarity with memory array design architectures, fab processes, and failure modes
• Ability to interpret DUT definitions and deliver completed TEGs
• Excellent problem-solving, interpersonal, and data-driven decision-making skills

Preferred Qualifications

• Proficiency in Perl, Skill code, and UNIX shell scripting languages
• Experience in design debug based on silicon learning
• Advanced knowledge of silicon processes, mask development, and OPC processes

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. We deliver a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products that fuel the data economy and enable advances in artificial intelligence and 5G applications.