Member of Technical Staff - Microarchitect/RTL Design

About the Company

Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.

Responsibilities

• Own the AI-driven microarchitecture and RTL design of mission-critical SoC blocks and sub-systems
• Define, drive, and revise block-level micro-arch specifications for fundamental HW accelerator blocks
• Own AI-driven RTL design flow end-to-end, from code generation to incorporating feedback from lint, CDC, synthesis, and timing closure
• Work with the principal architect to refine specs and resolve implementation trade-offs
• Define and maintain interface specifications such as AXI, AXI-Stream, or custom protocols
• Build and maintain RTL infrastructure including design automation scripts and regression flows
• Collaborate with DV to support bring-up with reference models, assertions, and test-plans
• Support FPGA prototyping on Xilinx for early functional validation

Requirements

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field
• 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience
• Expertise in SystemVerilog with strong design habits like parameterization and modularity
• Hands-on experience with block-specific compute datapaths and data movement (MAC arrays, vector units, DMA engines, etc.)
• Solid grasp of SoC methodology including synthesis, timing constraints, CDC, and AMBA protocols
• Strong Python skills for design automation and regression infrastructure
• Experience taking a block from RTL through synthesis and working with PD teams on PPA closure

Preferred Qualifications

• Experience with low-power design techniques (clock gating, power gating, UPF)
• FPGA prototyping experience using Xilinx Vivado/Vitis
• Familiarity with SIMD/VLIW execution pipelines
• Experience writing SVA assertions and functional coverage
• Track record in R&D for energy-efficient, high-performance HW accelerators

Benefits

• Competitive salary and meaningful equity stake
• Fast-paced startup environment with autonomy and visible impact
• Cutting-edge challenges at the intersection of AI and silicon design