Member of Technical Staff, Formal Verification

Responsibilities

• Analyze architecture and design specifications to identify formal verification requirements
• Develop and execute formal verification plans for silicon, IP, and subsystems
• Build formal verification environments, SystemVerilog Assertions (SVA), and formal properties
• Perform property checking, model checking, equivalence checking, and deadlock/livelock analysis
• Debug formal verification failures and analyze counter examples
• Drive verification closure through formal coverage analysis and proof convergence
• Mentor junior verification engineers and provide technical leadership
• Collaborate with Simulation, Emulation, and validation teams

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 10+ years of experience in ASIC/SOC verification
• 7+ years of formal verification experience
• Strong understanding of digital design fundamentals and computer architecture
• Experience with Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
• Expertise in SystemVerilog Assertions (SVA) and formal properties
• Proficiency in scripting languages such as Tcl, Python, Perl, or Shell
• Strong debugging and root-cause analysis skills

Preferred Qualifications

• Knowledge of UVM and simulation-based verification methodologies
• Experience with CDC, RDC, low power verification, and equivalence checking
• Familiarity with GPU, high-performance computing, and memory-based architectures
• Prior technical leadership or mentoring experience

Benefits

• Competitive salary, performance-based bonus, and early stage equity grant
• Comprehensive health, dental, vision, and life insurance
• Relocation assistance and visa sponsorship
• Daily lunch stipend and 401k match

About the Company

Netpreme is an early-stage startup working on high-performance computing and memory acceleration for the Artificial Intelligence and DataCenter space.