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Architect
Posted 14 hours ago

Member of Technical Staff - Formal Methods

ArchitectMember of Technical Staff - Formal Methods

Perks & benefits

Education AllowanceHealth InsuranceRelocation AllowanceVisa

Requirements

PhD in CS or EECS, Expertise in temporal logic or SMT, Experience with TLA+, Lean, or Coq, Strong software engineering skills

Skills

SMT

About the role

About the Company

Architect is an AI lab for the compute stack, starting with chip design. We build AI systems to design on-demand custom ASICs at scale. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.

Responsibilities

  • Design and implement the formal specification language and intermediate representation for hardware specifications, testbench, assertions, and RTL
  • Build proof-obligation generators and toolchains to discharge claims via SMT solvers, model checkers, and proof assistants
  • Establish soundness arguments and coverage-adequacy methodologies to verify generated artifacts
  • Co-design with verification methodology and ML research teams to integrate formal layers into agent loops
  • Own the formal stack end-to-end, from spec language to solver integration

Requirements

  • PhD in Computer Science, EECS, or a closely related field with a focus on formal methods applied to hardware or systems
  • Deep expertise in at least two of: temporal logic/model checking, SMT-based verification, refinement-based specification, or proof assistants
  • Experience with formal frameworks such as TLA+, Lean, or Coq
  • Demonstrated history of applying formal methods to real-world shipped artifacts
  • Strong software engineering skills with experience in compiler-style infrastructure
  • Ability to turn research-grade ideas into production components on a chip-design timeline

Preferred Qualifications

  • Industrial formal verification experience at leading silicon companies or automated reasoning groups
  • Experience with High-Level Synthesis (HLS) tools
  • Background in compiler/IR design or DSL implementation
  • Publications at top formal methods, PL, or EDA venues (CAV, FMCAD, POPL, PLDI, TACAS, DAC, ICCAD, DVCon)
  • Familiarity with modern AI/ML systems and formal guarantees
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Member of Technical Staff - Formal Methods

Architect · Palo Alto

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