Member of Technical Staff - Compilers

About the Company

Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale, co-designing custom ASICs alongside evolving ML workloads to unlock capabilities impossible with current hardware paradigms.

Responsibilities

• Own the compiler stack targeting a SIMD/VLIW NPU, from graph ingestion through code generation on production silicon
• Implement the memory management layer, including scratchpad memory, data tiling, bank allocation, and DMA scheduling
• Design and iterate on mid-end and backend optimization passes such as operator fusion, loop transformations, and vectorization
• Co-design the ISA and instruction encoding with the architect and silicon team
• Support quantization and mixed-precision lowering for various precisions (FP32, INT8/4, BF16, etc.)
• Benchmark compiler output against cycle-accurate models, RTL simulation, and FPGA prototypes
• Grow into a compiler team lead as the team scales

Requirements

• Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, or a related field
• 5+ years of experience building compilers or code generation toolchains for custom accelerators
• Deep experience with ML/AI hardware compilers (e.g., Apple Neural Engine, Google XLA/TPU, Groq, Cerebras, Qualcomm Hexagon, or AMD AIE)
• Strong grasp of instruction scheduling, register allocation, and software pipelining for SIMD/VLIW architectures
• Experience with tiling strategies, loop nest optimization, and operator fusion for ML workloads
• Proficiency in C++ and Python
• Familiarity with MLIR or LLVM infrastructure

Preferred Qualifications

• Experience in HW/SW co-design and defining ISA features
• IR design for ML accelerators using MLIR or graph-level IRs like XLA HLO
• Experience with ML frameworks (PyTorch, TensorFlow) and ONNX
• Understanding of ML inference systems (FlashAttention, PagedAttention, KV cache management)
• Contributions to open-source ML compiler projects like TVM, MLIR, Triton, or XLA