Member of Technical Staff, ASIC Design

Responsibilities

• Responsible for RTL design of IPs, subsystems and SOCs supporting the silicon roadmap
• Provide technical leadership in defining IP/SOC microarchitecture specifications and design methodologies
• Conduct design reviews to ensure adherence to best practices
• Guide the team in optimizing designs to meet aggressive performance, power and area goals
• Drive collaboration with architecture, verification, physical design, firmware, DFT, and post silicon domains
• Interface with external IP vendors, foundries and EDA tool providers

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Minimum of 5+ years of ASIC/SOC digital design experience
• Strong knowledge of the full ASIC/SOC development cycle from microarchitecture to tape-out
• Technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification
• Hands-on design experience in industry standards such as Ethernet, UCIe, or UALink
• Proficiency with front-end development tools and scripting for automation

Preferred Qualifications

• PhD in Electrical Engineering, Computer Engineering, or a related field
• Experience managing relationships with external design partners, IP vendors, and foundries
• Knowledge of Design-For-Testability, post silicon debug, validation, or manufacturing test
• Experience with design and tapeout of advanced silicon devices

Benefits

• Competitive salary and performance-based bonus
• Early stage equity grant
• Comprehensive health, dental, vision, and life insurance
• Relocation assistance and visa sponsorship
• Daily lunch stipend and 401k match

About the Company

Netpreme is an early-stage startup working on advanced architecture for high-performance computing, specifically focusing on memory acceleration for LLMs in modern data centers.