Manager, Static Timing Analysis (STA)

Responsibilities

• Build, manage, and mentor a high-performing STA team to drive technical excellence and career development.
• Own end-to-end STA for FPGA designs, including constraint development, timing analysis, and timing signoff.
• Define and implement robust STA methodologies, flows, and best practices to improve timing convergence.
• Partner with RTL design, synthesis, physical design (P&R), and architecture teams to resolve timing issues.
• Drive improvements in performance, power, and area (PPA) through timing-driven design and optimization.
• Leverage industry-standard EDA tools to analyze timing, debug violations, and automate flows.
• Ensure on-time delivery of timing closure milestones across multiple programs.

Requirements

• 10+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs.
• 3+ years of experience managing or leading engineering teams.
• Deep knowledge of STA concepts including setup/hold, clock domain crossing (CDC), and timing constraints.
• Strong experience with timing signoff tools such as PrimeTime or equivalent.
• Solid understanding of synthesis, place & route (P&R), and full chip implementation flows.
• Proficiency in root-cause analysis of timing violations across complex designs.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

• Experience with FPGA architecture and design flows.
• Familiarity with advanced nodes and high-speed designs.
• Exposure to scripting and automation using Tcl or Python for timing analysis.
• Experience working in large-scale, distributed engineering environments.

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our broad portfolio of products, including FPGAs, CPLDs, and Intellectual Property, provides the flexibility to accelerate innovation in AI, data centers, and networking.