Manager, FPGA Synthesis

Responsibilities

• Build, manage, and mentor a high-performing synthesis engineering team to drive technical excellence and execution.
• Lead the development and optimization of synthesis algorithms, including logic optimization, mapping, and netlist generation.
• Own and enhance synthesis stages within the FPGA compiler to ensure seamless integration with placement, routing, and timing flows.
• Drive improvements in performance, power, and area (PPA) through advanced synthesis-driven optimizations.
• Guide the translation of high-level RTL (Verilog/SystemVerilog/VHDL) into optimized gate-level representations.
• Partner with architecture, placement, routing, and timing teams to align synthesis strategies with FPGA architecture.
• Oversee debugging of synthesis-related issues, including timing bottlenecks and logic inefficiencies.

Requirements

• 10+ years of experience in FPGA/ASIC design tools, with a strong emphasis on synthesis or logic optimization.
• 5+ years of experience managing or leading engineering teams.
• Deep understanding of logic synthesis, optimization techniques, and mapping algorithms.
• Strong knowledge of RTL design (Verilog, SystemVerilog, or VHDL).
• Proficiency in C/C++ and software engineering best practices.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Preferred Qualifications

• Experience with FPGA toolchains such as Quartus or Vivado.
• Understanding of FPGA architectures, including LUTs, DSPs, BRAM, and routing resources.
• Experience with advanced optimizations like retiming, resource sharing, and logic restructuring.
• Familiarity with scripting languages such as Python or Tcl for automation.
• Background in large-scale, distributed EDA development environments.

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products includes FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs, and IPUs.