Machine Learning R&D

Responsibilities

• Lead Machine Learning R&D efforts in Generative AI and Agentic AI to optimize chip design processes and hardware engineering workflows.
• Oversee the design and delivery of internal benchmark suites for LLMs and Agentic AI specifically for hardware design applications.
• Identify and pursue impactful technical research directions for GenAI applications in hardware design.
• Provide technical leadership and coaching to an interdisciplinary team of ML researchers, software engineers, and hardware designers.
• Define and update technical project goals, roadmaps, and innovation engines from idea to execution.
• Collaborate with cross-functional teams to identify technical gaps and opportunities.

Requirements

• PhD in Computer Science, Electrical Engineering, or a related field.
• 5+ years of industry experience in Machine Learning, Generative AI, and MLOps.
• Proficiency in programming languages such as Python, Java, or C++.
• Hands-on expertise with machine learning frameworks like TensorFlow or PyTorch.
• Deep experience with Agentic AI tools and frameworks (e.g., Langchain, Agno, or similar).
• Proven track record in ML/AI product development and deployment.

Preferred Qualifications

• Experience with LLM and agentic AI post-training optimization.
• Expertise in embedding models and foundational model architectures.
• Experience working in interdisciplinary environments involving VLSI design or hardware engineering.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Comprehensive health benefit options for employees and dependents.
• Wealth-building programs and financial security resources.
• Wellbeing programs and continuous learning/development opportunities.

About the Company

Qualcomm is a global leader in wireless technology, developing products that power the world's most advanced mobile and connected devices. Our Applied ML R&D team works at the intersection of AI and hardware design to drive innovation in the chip design process.