Lead Physical Design Engineer

Responsibilities

• Lead the physical design and implementation of complex, high-performance semiconductor integrated circuits for AI NPUs
• Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis (CTS), and static timing analysis (STA)
• Collaborate with physical verification and power integrity teams to resolve DRC, LVS, antenna, IR drop, and EM issues
• Partner with design, verification, and DFT teams to ensure seamless integration and project milestone achievement
• Analyze and resolve design issues related to timing, area, and power
• Develop and maintain scripts for automation and continuous improvement of physical design methodologies and flows
• Generate comprehensive reports and documentation of design implementation

Requirements

• Bachelor's or Master's degree in VLSI, Electronics Engineering, or a related field
• Minimum 8 years of experience in digital physical design of complex SoCs or ASICs
• Proficiency with industry-standard EDA tools such as Cadence Innovus/Genus/Tempus or Synopsys Fusion Compiler/PrimeTime
• Solid understanding of floorplanning, placement, routing, clock tree synthesis, and physical verification
• Strong knowledge of Static Timing Analysis (STA) and timing closure techniques
• Proficiency in scripting languages including Tcl, Perl, or Python
• Familiarity with deep sub-micron process technologies
• Excellent problem-solving skills and ability to work in a collaborative team environment

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.