Lead IP Block level Verification Engineer

Responsibilities

• Lead and plan the verification of complex digital design blocks by analyzing architecture and design specifications
• Partner with architects and design engineers to develop comprehensive verification testplans
• Architect and design testbenches using SystemVerilog and UVM for efficient design verification
• Create and enhance constrained-random and directed verification environments
• Utilize System Verilog Assertions (SVA) and formal tools to verify designs
• Debug complex tests in collaboration with design engineers to ensure functional correctness
• Identify coverage measures and perform analysis to achieve closure on coverage metrics

Requirements

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering
• 8+ years of experience in digital design verification
• Expert-level proficiency in SystemVerilog and UVM
• Hands-on experience with simulation and debug tools such as Synopsys VCS or Cadence IES
• Deep understanding of the various phases of ASIC development

Preferred Qualifications

• Experience with block-level Network on Chip (NOC) verification
• Knowledge of industry protocols including AXI3/4, DDR4/5, HBM, or PCIe
• Experience with formal property checking tools like Jasper or Synopsys VC-Formal
• Background in verification architecture, establishing methodologies for high-performance SOCs or FPGAs
• Familiarity with gate-level simulation, power verification, and reset verification

About the Company

AMD is a global leader in high-performance computing, graphics, and visualization technologies. Our mission is to build products that accelerate next-generation computing experiences, ranging from AI and data centers to gaming and embedded systems. We foster a culture of innovation, collaboration, and execution excellence.