Layout Verification/PEX Engineer

Responsibilities

• Run established DRC, LVS, ERC, antenna, density, and parasitic extraction flows using existing scripts, runsets, and foundry PDK decks.
• Validate electrical routing in photonic integrated circuit layouts, including routing for photonic devices, bias lines, heaters, phase shifters, modulators, monitor structures, control signals, and electrical I/O interfaces.
• Generate extracted netlists and extracted views for post-layout electrical simulation.
• Maintain organized logs, reports, run directories, and status trackers.
• Support block-level and chip-level verification activities prior to tapeout.

Requirements

• Bachelor's degree in Electrical Engineering, Physics, Microelectronics, or related field, or equivalent experience.
• Basic knowledge of IC layout and physical verification concepts.
• Exposure to DRC, LVS, or parasitic extraction.
• Familiarity with Linux or Unix environments.
• Strong attention to detail and ability to follow established procedures.
• Good communication and documentation skills.
• Demonstrated interest in quantum computing.
• Ability to contribute in a fast-moving start-up environment.

Preferred Qualifications

• Exposure to analog/mixed-signal ICs, or custom IC layout.
• Experience with Cadence Virtuoso, Siemens Calibre, Cadence Pegasus/PVS, Cadence Quantus, and similar EDA tools.
• Familiarity with post-layout simulation flows and extracted netlists.
• Basic scripting experience in Python.
• Exposure to silicon photonics, photonic integrated circuits, or optoelectronics.
• Demonstrated interest in quantum computing, silicon photonics, or advanced semiconductor technology.

About the Company

PsiQuantum is building the first useful quantum computers using silicon photonics. The company leverages semiconductor manufacturing to develop million-qubit, fault-tolerant quantum systems and collaborates with GlobalFoundries and Fortune 500 partners to prepare quantum solutions for real-world impact.