Layout Engineer

Responsibilities

• Build block-level layouts in Cadence Virtuoso, including floorplanning, placement, routing, and optimization
• Apply layout methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy
• Ensure DRC, LVS, density, and reliability compliance
• Support parasitic extraction, post-layout verification, and ECO activities
• Create partial custom layouts for selected device-level or small analog blocks

Requirements

• Experience performing physical layout using Cadence Virtuoso or similar tools
• Familiarity with DRC, LVS, physical verification, and reliability checks
• Ability to plan, document, and review layout goals with cross-site teams

Preferred Qualifications

• Experience with DRAM, memory circuits, or large hierarchical designs
• Background in parasitic extraction flows and post-layout optimization
• Hands-on experience with partial custom layout for devices or small analog circuits
• Strong communication skills supporting global engineering teams

Benefits

• Choice of medical, dental, and vision plans
• Income protection programs for illness or injury
• Paid family leave
• Robust paid time-off program and paid holidays

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.