Layout Design, Staff Engineer

Responsibilities

• Lead the design and development of next-generation DDR and HBM PHY IP layout.
• Provide technical mentorship and guidance to junior engineers to foster skill development.
• Take ownership of layout planning, execution, and quality review processes.
• Collaborate with cross-functional teams including circuit design, verification, and product engineering.
• Manage effort estimation, project scheduling, and execution in multi-disciplinary settings.
• Review and optimize layout for advanced process technologies (CMOS, FinFET, GAA) ensuring compliance with DFM, EMIR, and reliability standards.
• Support critical phases such as floorplanning, LEF generation, and bond-pad layout.

Requirements

• BTech/MTech degree in Electronics, Electrical Engineering, or a related field.
• Minimum 5 years of relevant experience in physical layout design.
• Deep expertise in advanced process nodes (7nm and below).
• Strong command of deep submicron effects and advanced floorplan techniques.
• Expertise in CMOS, FinFET, and GAA process technologies.
• Proficiency in layout matching, ESD, latch-up, PERC, EMIR, DFM, and LEF generation.
• Proficiency in using industry-standard EDA tools for layout and verification.

Benefits

• Comprehensive medical and healthcare plans.
• Paid time away including ETO and FTO programs.
• Family support including maternity/paternity leave and adoption assistance.
• Employee Stock Purchase Plan (ESPP) with a 15% discount.
• Competitive salaries and regional retirement plans.

About the Company

Synopsys is a leader in chip design, verification, and IP integration. Our technology is central to the Era of Pervasive Intelligence, driving innovations in fields ranging from self-driving cars to learning machines. Our Silicon IP business provides the world's broadest portfolio of predesigned blocks to help customers bring differentiated products to market quickly.