Layout Design Staff Engineer

Responsibilities

• Lead the development of cutting-edge DDR and HBM layout IPs, setting technical direction and standards.
• Provide hands-on expertise in layout creation, problem-solving, and technical troubleshooting.
• Mentor and guide junior engineers, fostering growth and technical excellence within the team.
• Estimate project efforts, plan schedules, and execute projects in cross-functional settings.
• Collaborate with teams to support critical layout requirements, floorplanning, and quality assurance processes.
• Conduct layout reviews to ensure compliance with release processes and stringent customer requirements.

Requirements

• BTech/MTech in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in layout design, specifically in DDR & HBM PHY IP development.
• Deep understanding of submicron effects and floorplan techniques in CMOS, FinFET, and GAA technologies (7nm and below).
• Expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame/pitch requirements.
• Strong ability to lead projects, manage schedules, and ensure product quality within tight timelines.
• Excellent written and verbal communication skills.

Benefits

• Comprehensive medical and healthcare plans.
• Paid time away including ETO and FTO programs.
• Family support including maternity/paternity leave and adoption assistance.
• Employee Stock Purchase Plan (ESPP) with a 15% discount.
• Competitive salaries and regional retirement plans.

About the Company

Synopsys drives the innovations that shape the way we live and connect. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content for the Era of Pervasive Intelligence.